The Trend Toward Lower-Cost Semiconductor Test Equipment

Implications: There is a trend toward lower-cost STE.  Despite the article's assertion that certain device functions don't lend themselves well to design for test (DFT) techniques, the largest cost item in an STE tester is the digital subsystem, and the digital part of a device is well suited to DFT.

This trend will improve the return on investment for users of semiconductor test equipment, but will hurt the equipment vendors as they suffer revenue compression and have to focus their digital engineering groups on lowering cost, rather than chasing premium-priced performance.

Analysis:

Throughout most of the history of semiconductor test equipment development, the design trend was toward greater performance at continually increasing cost. This was driven primarily by the need to stay ahead of the external data rates and parametric test requirements of successive generations of new devices. Particularly in the logic portion of semiconductor devices, increased computing power and improved data communication bandwidth led to greater numbers of higher-speed digital device pins; pins which needed to be connected to equivalent digital channels on the test equipment.

Continually chasing Moore's Law in this fashion led to the development of 1024-pin testers capable of data rates in excess of 3.2Gb/s per pin, and average selling prices of close to $2m. Fully-configured testers could easily top $4m.

Following the 2001 industry decline this trend stopped, and a permanent quantum step down in performance and cost has been established. Testers today sport digital channels capable of data rates in the 200Mb/s to 400Mb/s range, augmented by a few specialized high-speed pins where required, with average selling prices below $1m. This has been enabled by:

• The trend toward inter-device communication taking the form of a reduced number of high-speed serial links, replacing wide, parallel buses. This reduces the number of tester resources that must be capable of high-speed data and parametric test capability, and significantly reduces the cost.

• An increased use of DFT (design for test) and BIST (built in self test) techniques at the design stage, that takes more of the overall test burden from the external tester and places it on-chip.

• The transformation of a previously differentiated portion of the tester (its digital channels) into a commodity.

• Greater recognition that the test process is intended to catch manufacturing defects, not characterize the device or validate its performance (an exception to this is performance binning).

In addition to lowering the capital cost, this trend will also extend the lifetime of test equipment, as increasing device performance does not automatically lead to an obsolescence of the installed base, as it did in the past.