Sandisk 3-Bit per Cell Technology Enables Larger, Less Expensive Flash Memory

Implications: * Sandisk announced that they will start shipping 3-bit per storage cell NAND flash memory in March or April, 2008 * Currently the densest flash memory is 2-bit per cell multilevel cells (MLC) * The technology was co-invented with long-time Sandisk partner, Toshiba * The technology will be used on 16 Gb NAND flash chips using 56 nm photolithography and with 8 MBps write rate * Sandisk says that an advanced architecture for the storage devices allows them to achieve higher storage capacities without sacrificing performance or reliability

Analysis: Flash memory has been available for the last few years with single level cells having one bit of storage per cell (SLC) and 2-bits per cell multilevel cell (MLC).  The SLC memory is inherently more reliable but it is more expensive per bit of memory.  Improvements in the controller and memory architecture led to the ability to create multiple voltage levels per cells allowing more than one bit to be stored per flash memory cell.   

The write wear is worse as the number of levels in the cell are increased so the multilevel cell flash memory has to incorporate wear-leveling technology to try and wear the memory cells more evenly through the device.  The write performance is also worse for multi-level cells.  In order to provide faster write/read performance the flash memory must be organized to work in parallel so the net data is increased by the number of parallel lines of memory being used at one time. 

The wear leveling and parallel access are functions of the flash controller that stands between the host system and the flash memory cells.  Thus the key to advances in multi-level flash memory are more advanced flash controller technology.   If Sandisk can make good on its claim of equivalent reliability and performance with 3-bits per cell to 2-bits per cell then the company will have an advantage in the price per GB compared to flash memory companies that don’t have access to this technology. 

3-bit per cell technology requires no change in the basic design of flash memory from a manufacturing viewpoint, only in the architecture and controller side.  Thus the cost reductions per bit can be significant using 3-bits per cell (maybe 50% or greater cost reduction are possible).  With changes in manufacturing flash cell density alone (without the use of 3-bit cells) the cost per bit reduction may be about 30% annually so 3-bits per cell could lower the manufacturing costs for Toshiba and SanDisk significantly more than their competitors.  

SanDisk’s expertise in flash controllers was enhanced by their acquisition (completed last year) of M-Systems.  M-Systems had been working on multiple bit per cell technology before they merged with SanDisk.  It will be interesting to see what the response to this development is at other flash memory suppliers such as Samsung, Intel/Micro and (reportedly) Seagate. 

3-bit per cell flash will probably find its first home in consumer devices and USB storage devices.   Computer system manufacturers are still leery about using multi-level cell flash in enterprise and laptop applications.