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April 23, 2007

IBM development will increase demand for performance test at probe

Analysis of: IBM Develops Chip-Stacking Technique | www.eweek.com
This analysis is solely the work of the author. It has not been edited or endorsed by GLG.
Analysis By:
Neil Kelly, Semiconductor Test ConsultantNeil Kelly
Semiconductor Test Consultant, Neil Kelly
Implications: The use of stacked die in a single chip will drive an increase in demand for known good die, which in turn will increase the focus on test at the probe stage.  This will change the accepted strategy in non-memory devices of a crude test to prevent packaging bad die into one of performance test at probe, as there will no longer be package test as a backstop.

Analysis: Stacking multiple die into a single package is an established trend in memory devices, where different memory types such as DRAM, SRAM and flash may be combined to save printed circuit board area.  IBM's development extends and refines that technique to non-memory devices, and this will drive a move to an increased level of testing at the probe stage (while removing entirely the package test).  This trend will benefit advanced probe card manufacturers such as Formfactor and Cascade Microtech who have the interconnect technology to enable high performance test at probe.  There will be a corresponding reduction in demand for the high-performance contactors used in package test.  Unfortunately for the test equipment vendors, it will also reduce the total amount of test required and the demand for their equipment.

Other Analyses of the Same Source Article:
IBM stacks chips, wins power savings
April 19, 2007, Author: Cliff Bell, Chief Information Officer, Infogain Corporation

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