CMP – Still Sorting Out the Last 50 Years

Implications: The first 50 years of IC technology were a remarkably rapid convergence of new concepts, sophisticated technologies, defect reduction and control, yield improvement, and reliability understanding and improvement. This academic list includes processes for silicon crystal growth and wafer fabrication, photolithography, thin film deposition, plasma etching, ion implant, diffusion, annealing, planarization, cleaning and the metrology to control them all. Many careers and companies have been built around these and all of the support infrastructure needed to turn this technology into a profitable enterprise.

Analysis: In fairness, there were another 10 years of prior semiconductor technology history before the launch of Solid State Technology. The very facts that the basic transistor itself was only invented in 1947, and it wasn’t even made out of silicon, AND it warranted the birth of an industry trade magazine of its own in 1957, make the origins of the silicon integrated circuit industry all the more remarkable. When an idea is that good, people of vision can rally around the cause in numbers sufficient to make things happen now.

Today, it’s so easy to take sophisticated electronics for granted because user interfaces, packaging, software and marketing have all conspired to make these devices such an integral part of our daily personal and business lives. Slow down for a moment and take the time to be amazed! We really do all work in an impressive industry.

During those first ten years of semiconductor technology, the transistor evolved from a point contact device in bulk germanium to a planar transistor in silicon. This puts the roots of silicon chemical mechanical polishing (CMP) very close to the origins of integrated circuits as we know them today. This also puts some of the earliest suppliers of CMP technology close to the origins of the IC industry. Some of them are still active today.

But it wasn’t until 1983 that chemical mechanical polishing (CMP) evolved into chemical mechanical planarization (CMP). At this point, I am compelled to back-pedal ten years to the 40^th Anniversary Issue of Solid State Technology, in which I had the honor of writing an article about “The Early Days of CMP.” In my youthful ignorance, I identified a group in the IBM East Fishkill Base Technology organization as the birth parents of CMP. I have since been advised that they were actually the adopting parents. The birth parent (for those of you who were paying attention in Biology 101, this is known as asexual reproduction) was another denizen of IBM East Fishkill from the other side of the facility in the silicon wafer plant.

Klaus D. Beyer is the source of the concept for using polishing technology for planarization in IBM. He had been developing bare silicon wafer polishing and cleaning methods since 1981, and had come to the conclusion that megasonic cleaning was better for removing particles and reducing surface scratches than the brush cleaning that was widely used at the time. This project was diverted, however, and Klaus was asked to assist on a project to replace thermal oxidation with a low stress oxide fill process for device isolation. This later evolved into the trench isolation we know today, but before that could happen, the oxides filling the trenches needed to be planarized. No sane person in those days would have suggested taking a pristine silicon device wafer back into the particle-filled environment of a polishing process. The reason that Klaus thought he could do so and still be considered sane was that he had just taught himself that those particles can be reliably cleaned off of the wafer without causing any damage. And thus CMP was born.

The project was staffed shortly thereafter in the Base Technology group, and the original trench isolation objective was expanded to include planarization of oxide dielectrics over aluminum interconnects. To the outside world, it appeared that shallow trench isolation followed years behind oxide and tungsten planarization, but now we all know that it was STI – and Klaus Beyer – who were there first.

Or were they? I still have the nagging memory of a conversation I had many years ago with Jerry Zimmer, now CTO of sp³ Diamond Technologies. He told me of a chemical mechanical planarization project at Raytheon that dated back to about 1974. Neither of us could ever find the reference, and we dropped it. So the clock is ticking, people. You have another ten years to send me this lost information so I can print another correction in the 60^th Anniversary Issue.

Looking forward to the next 50 years of CMP is an exercise better left to those actually still developing device architectures, because this is ultimately from where the inventive sparks will come. The decades of pushing more and more development work out of the fabs and into the suppliers has limited utility; it is better suited for improving manufacturing productivity and the supply chain infrastructure for equipment and the materials needed for known processes. The new device architectures needed to challenge Moore’s Law another generation or two won’t be developed by a single supplier, or even by a vast consortium of suppliers. A device developer will always be needed to pick a direction, develop a concept or two, throw out the ones that aren’t going to work in the real world, and convince other chip makers and suppliers that this is the way to go.

We’re seven years into The Decade of Materials. We might call the next ten years The Decade of Nanotechnology, or The Decade of Self-Assembly. Whatever you want to call it, this coming decade is about all you can put a label on right now. The next forty years beyond that are still a bit hazy.