GLG News by Neil Kelly

Implications: Industry consolidation in this case will not lead to a reduction in available products in the short term, so is of little immediate benefit to the industry as a whole.  Verigy will be the strongest out of the remaining SOC test companies as they alone benefit from the economics of single platform, and will compete with a Teradyne that is financially weaker after the Eagle acquisition.  Eagle doesn't have any test technology that isn't already part of Teradyne's FLEX platform - indeed Teradyne has recently beaten Eagle in head-to-head competition.

Analysis: The formation by merger of LTX-Credence has driven Eagle Test to find a suitor to rescue it from being the sole tier 3 semiconductor test vendor - Teradyne obliged by providing a coup de grace for Len Foxman.  Continuing the products and support at Eagle's customers allows Teradyne's executives to claim that the acquisition will be accretive in 2009, even though they have no idea what business conditions will be like next year, and assuming that neither of the customers who currently buy Eagle products do so precisely because they aren't Teradyne.

Implications: Two tier 2 companies forced together by weakness creates another tier 2 company.  The combination will reduce number of test platforms in the industry and enhance the profitability of Teradyne and Verigy.

Analysis: Combining two companies out of weakness is rarely a solution to competition from strong companies.  Management of both companies will be consumed with the merger, employees will be distracted as they wonder if they are part of the cost savings, and customers will be wooed by the competition.  Teradyne and Verigy will be visiting every LTX and Credence customer to tell them that their product will be discontinued by the combined company.  Unless the product road map has already been decided, every customer is potentially in play.  If there is a combined product road map, and it is communicated to customers, then those who currently buy the discontinued products are in play.  Either way, customer leakage, possibly significant, is likely to occur.  

Sapphire will likely be canceled - it's R&D is expensive, and the market has moved on from this kind of tester.  Although it has represented a large portion of Credence revenue, that share has been declining, and those customers (one large one) will likely be lost to Teradyne or Verigy.  The ASL3000 variants will be canceled since they are a direct overlap with the Fusion X series.  Diamond's fate will depend on how much engineering work is required to finish it, although it does offer a high pin count, low cost test platform that LTX lacks.  The ASL1000 has a large installed base, and is popular in Asia, but it's age is likely to provide support headaches with component obsolescence.

The company that invented the single-platform concept (LTX) that has now been embraced by the rest of the industry now has more incompatible test platforms than the rest of the industry combined.  Combining LTX and Credence will help industry revenue and profits by reducing the number of test platforms.  Teradyne and Verigy will be the primary beneficiaries of that improved business climate.

Implications: Advantest has acquired the remnants of SZ from Credence, giving them power and analog testers and some incremental customers.  The technology won't be integrated into Advantest's SOC platforms - if that's why Advantest bought it, they're fooling themselves.  Credence continues the divestment of assets acquired by their former management team who dreamt of being a tier 1 ATE company.

Analysis: Credence bought the assets of SZ Testsystems in 2002 for $4.7m, saving it from a bankruptcy filing.  The test technology they acquired was mostly analog and power, and their key customers were automotive, so the unit became Credence's automotive division.  None of the technology was incorporated into Credence's other products, and the same will be true with Advantest, no matter what management may say.  Moving test technology between incompatible platforms never happens in this industry - the engineering effort is always underestimated, and any instruments that are attempted to be ported are eventually redesigned.  Advantest has valued the asset at about the same as Credence did almost six years ago in nominal terms; Credence would probably have been willing to give it away.

Implications: Teradyne gets a capable entry into flash memory test to allow the company to compete more effectively against Verigy.  Nextest executives get over being swallowed for a second time by Teradyne by negotiating a good price for the company.  Keeping Nextest key employees will be the challenge.

Analysis: Teradyne's acquisition of Nextest is a good strategic fit for the company.  Teradyne's gets a well-architected flash memory tester and an established customer base that they can drive to greater success with their field organization.  In addition, it's likely there will be development synergies with FLEX in future generations beyond Magnum., together with the Mosaid assets Teradyne acquired earlier.

Teradyne will now be able to take the fight to Verigy's turf in flash memory test instead of just playing defense in the SOC space.  The Magnum is a worthy competitor to Verigy's Versatest series, and will automatically be considered by more customers now it's backed by a company like Teradyne.

Keeping Nextest's key employees will be Teradyne's main challenge.  The company's executives are from the Q2 memory group of Megatest, and left when Teradyne bungled the acquisition of that company in the early '90s.

Implications: Acquisition weakens the power of Verigy's single platform strategy.  Demonstrates the failure of standalone structural test in the commercial test marketplace.  Financial terms are not disclosed, so price should be close to zero.

Analysis: Verigy no longer has a single platform solution to SOC test, and Inovys won't provide enough benefit to offset the damage to that strategy.  Standalone structural testers have not displaced conventional testers for SOC, and have been limited primarily to debugging first silicon in the lab.  As a different platform than the 93K, any application developed on the Ocelot will not even act as a feeder to the 93K production tester.  Structural test techniques are well understood, and are incorporated into all SOC testers as part of their overall test suite, so it's unlikely that Inovys brings any technology that Verigy didn't already have.

Implications: The use of stacked die in a single chip will drive an increase in demand for known good die, which in turn will increase the focus on test at the probe stage.  This will change the accepted strategy in non-memory devices of a crude test to prevent packaging bad die into one of performance test at probe, as there will no longer be package test as a backstop.

Analysis: Stacking multiple die into a single package is an established trend in memory devices, where different memory types such as DRAM, SRAM and flash may be combined to save printed circuit board area.  IBM's development extends and refines that technique to non-memory devices, and this will drive a move to an increased level of testing at the probe stage (while removing entirely the package test).  This trend will benefit advanced probe card manufacturers such as Formfactor and Cascade Microtech who have the interconnect technology to enable high performance test at probe.  There will be a corresponding reduction in demand for the high-performance contactors used in package test.  Unfortunately for the test equipment vendors, it will also reduce the total amount of test required and the demand for their equipment.

Implications: BIST (built in self test) is an important tool as part of an overall test suite, but today is largely a commodity that economically cannot stand alone as a product.  Logicvision has tied its fortunes to BIST, and cannot compete with the larger EDA companies that provide BIST as part of their integrated test offerings.

Analysis: When BIST is combined with design for test (DFT) techniques and external test, a comprehensive test strategy can be designed for new devices.  An optimized test suite for each device design will employ differing amounts of each of the three components depending on a variety of factors, but BIST cannot be the entire solution.  Designers who use EDA tools from one of the major suppliers are unlikely to go to Logicvision for the BIST component when an integrated version is already available from their EDA supplier.

Implications: The use of stacked die in a single chip will drive an increase in demand for known good die, which in turn will increase the focus on test at the probe stage.  This will change the accepted strategy in non-memory devices of a crude test to prevent packaging bad die into one of performance test at probe, as there will no longer be package test as a backstop.

Analysis: Stacking multiple die into a single package is an established trend in memory devices, where different memory types such as DRAM, SRAM and flash may be combined to save printed circuit board area.  IBM's development extends and refines that technique to non-memory devices, and this will drive a move to an increased level of testing at the probe stage (while removing entirely the package test).  This trend will benefit advanced probe card manufacturers such as Formfactor and Cascade Microtech who have the interconnect technology to enable high performance test at probe.  There will be a corresponding reduction in demand for the high-performance contactors used in package test.  Unfortunately for the test equipment vendors, it will also reduce the total amount of test required and the demand for their equipment.

Implications: Keith Barnes expounds on the advantages of the single, scalable platform, but in talking about how Verigy continues to drive down the cost of test misses the key factor causing tester price compression.

Analysis: The most expensive part of ATE test equipment by function is the digital subsystem, both in terms of vendor COGS and customer price.  This cost has been driven down principally by reduced external testing requirements from new chip designs, effected by combinations of built in self test (BIST) and design for manufacturing techniques - resulting in a "commodity" 200MHz digital pin being offered by every ATE vendor for their test platforms that can satisfy those reduced requirements.  The higher level of integration that Keith mentions is cost advantageous for large devices, or for testing multiple devices in parallel, but not all mixed signal devices lend themselves to high levels of parallel test.  Smaller numbers of instruments per card that allow more focused configurations and cheap digital pins are more effective at lowering cost for these devices.  Examples of these are wireless (especially those including RF) and consumer devices.

Implications: The purchase by Teradyne of memory test technology from Mosaid will help their move back into the memory test business.  Teradyne had been a secondary (to Advantest) DRAM test supplier through the 1980s and 1990s, but exited the business as part of their focus on SOC test and subsequent product line consolidation.  A brief attempt to position a version of the J750 as a flash memory tester was also discontinued.

Analysis: Teradyne management hinted on their last quarterly conference call (01/25/2007) at a move into memory test, by saying they would leverage product developments in their Flex SOC test family toward a new market.  Memory test, probably high-speed DRAM or possibly NAND flash, is the logical extension of instrumentation in the Flex.  Verigy extended their 93K SOC tester into high-speed DRAM test in a similar fashion.  The acquisition of Mosaid's memory test assets seems to confirm that direction.

Implications: Excess capacity, lower margins and price compression among the NAND flash producers will severely constrict investment in capital equipment.  A tough year for the device manufacturer will translate into a catastrophe for the flash test vendors.

Analysis: There are two principal drivers for purchases of semiconductor test equipment: increased capacity and technology change.  By far the largest of these is capacity, and if there was excess investment in 2006, as the article claims, there will be little of this kind of business in 2007.  In addition, technology change in flash test equipment in the past few years has been driven by the change from NOR to NAND, and improved productivity that has given the flash producers essentially free extra capacity.  A technology change in nonvolatile storage that would lead to a large-scale changeover of installed test equipment is, at best, several years away.

Implications: There is a trend toward lower-cost STE.  Despite the article's assertion that certain device functions don't lend themselves well to design for test (DFT) techniques, the largest cost item in an STE tester is the digital subsystem, and the digital part of a device is well suited to DFT.

This trend will improve the return on investment for users of semiconductor test equipment, but will hurt the equipment vendors as they suffer revenue compression and have to focus their digital engineering groups on lowering cost, rather than chasing premium-priced performance.

Analysis:

Throughout most of the history of semiconductor test equipment development, the design trend was toward greater performance at continually increasing cost. This was driven primarily by the need to stay ahead of the external data rates and parametric test requirements of successive generations of new devices. Particularly in the logic portion of semiconductor devices, increased computing power and improved data communication bandwidth led to greater numbers of higher-speed digital device pins; pins which needed to be connected to equivalent digital channels on the test equipment.

Continually chasing Moore's Law in this fashion led to the development of 1024-pin testers capable of data rates in excess of 3.2Gb/s per pin, and average selling prices of close to $2m. Fully-configured testers could easily top $4m.

Following the 2001 industry decline this trend stopped, and a permanent quantum step down in performance and cost has been established. Testers today sport digital channels capable of data rates in the 200Mb/s to 400Mb/s range, augmented by a few specialized high-speed pins where required, with average selling prices below $1m. This has been enabled by:

• The trend toward inter-device communication taking the form of a reduced number of high-speed serial links, replacing wide, parallel buses. This reduces the number of tester resources that must be capable of high-speed data and parametric test capability, and significantly reduces the cost.

• An increased use of DFT (design for test) and BIST (built in self test) techniques at the design stage, that takes more of the overall test burden from the external tester and places it on-chip.

• The transformation of a previously differentiated portion of the tester (its digital channels) into a commodity.

• Greater recognition that the test process is intended to catch manufacturing defects, not characterize the device or validate its performance (an exception to this is performance binning).

In addition to lowering the capital cost, this trend will also extend the lifetime of test equipment, as increasing device performance does not automatically lead to an obsolescence of the installed base, as it did in the past.